The present invention relates to the control of power expenditure in electronic circuitry, and more particularly to the control of clock frequency and voltage supply operating points in electronic circuitry.
Dynamic voltage and frequency scaling (DVFS) is a well-known principle in electronic circuit design: Clock frequency as well as voltage supply are scaled to the minimum values necessary to satisfy application performance requirements. Power savings occur across the total hardware component (not only at the clock related circuitry as for clock gating and frequency scaling techniques) and are significant due to the quadratic effect that voltage changes have on power consumption. A DVFS operating point (OPP) is defined by a predetermined clock frequency/voltage level pair. Several, or at least two, OPPs are defined for circuitry employing DVFS, with one of the OPPs being operative at any given time.
For a given circuit/component, selection of an OPP is made on a per application use case basis. Examples of use cases include, but are not limited to:                a phone being used for making a call        a phone being used for web browsing        a phone being in idle mode (i.e., switched on but not being used and capable of responding to an incoming call        
Selection of an OPP for a given use case is guided by the following principles:                It is desired to avoid selecting an OPP having too low a clock frequency and/or too low a supply voltage value because this may cause violation of application real-time constraints.        It is desired to avoid selecting an OPP having a clock frequency and/or supply voltage value higher than that which is required to satisfy application requirements because this results in higher than necessary energy consumption. This is due to the fact that the higher the clock frequency, the higher the required supply voltage value, and this higher supply voltage value in turn results in higher energy consumption.        
The inventors of the subject matter described herein have recognized that there are a number of problems with existing DVFS technology. One is that, with a limited number of defined OPPs, the mapping of application use cases to OPP may not be optimal. For example, assume that an embodiment has two defined OPPs, with OPP1 calling for a clock frequency of 100 MHz and OPP2 calling for a clock frequency of 50 MHz. Use cases that map to OPP1 (i.e., those with requirements calling for a clock frequency greater than 50 MHz) will therefore not benefit from DVFS because there will be no power reduction.
With the two OPPs as described, sub-optimal performance results because the worst case real time deadline within a use case will cause selection of the effective OPP to be OPP1 even if most of the time the use case can be running at a lower frequency.
Another detriment is that OPP frequency and voltage may be set early on in a project based on estimations of application requirements. Later on, due to changed requirements, the frequency and voltage may not be optimal from a power consumption perspective. It is therefore desired to have methods and apparatuses that achieve more optimal performance under the changed requirements.
The inventors of the subject matter described herein have further recognized that often a higher clock frequency is needed only for a very short period of time. However, switching from one OPP to another during this short period of time might result in significant overhead if OPP switching is implemented by means of a software-controlled processor.
An example of this problem arises in the context of the Long Term Evolution (LTE) system's “Micro Sleep”. The basic idea is to power-down the receiver path in the radio as soon it is detected that no data packet needs to be received in the current transmission time interval (TTI). This requires decoding of the control channel as fast as possible using the highest possible clock frequency. In this use case, OPP1 is required only during decoding of the control channel. The remaining time, OPP2 can be used. As control channel decoding takes only a very short amount of time, changing from one OPP to another in a software-controlled implementation would cause a lot of overhead.
It is therefore desired to provide DVFS control mechanisms that provide for the use of optimal OPPs without the overhead found in conventional implementations.